Shubham Draveriya Resume

Shubham Draveriya

RTL design and embedded systems engineer

I build RISC-V processors in Verilog, debug them waveform by waveform, and bring them up on FPGA boards. Keep scrolling and I'll take the chip apart for you.

See the RV32I core GitHub profile

I like hardware that has to work the first time.

I'm an M.Tech VLSI student working on frontend VLSI, RTL design and embedded systems: CPU microarchitecture, RISC-V processors, FPGA-based systems and the low-level seam where hardware meets software.

The part I enjoy most is bring-up. Writing the Verilog, running assembly on a core I built, staring at waveforms until the bug gives itself away, then fixing it for real.

Studying
M.Tech, VLSI design
Main areas
RTL design, CPU microarchitecture, verification
Also
FPGA prototyping, hardware–software integration
Based in
India

A RISC-V core, written from scratch

A complete RV32I processor in Verilog with its own control logic and datapath, verified by running assembly programs directly on the core and checking every writeback in the waveforms.

Follow one instruction through the core. The matching block lights up on the die.

The program counter drives instruction memory and a 32-bit instruction comes back.

Built

  • Instruction fetch, decode, ALU, register file and writeback
  • Control flow for branches, jumps and program termination

Debugged

  • Register writeback integrity across instruction classes
  • Control-flow hazards, traced through waveform timing

Tools

  • Verilog HDL
  • Icarus Verilog
  • GTKWave
  • RISC-V assembly
Source on GitHub

On the bench right now

  • Pipelined RISC-V core

    In progress

    Taking the RV32I design to a pipeline: stages, forwarding and stall control, while tracking data hazards, flush behaviour and timing closure.

    Verilog HDL, GTKWave, FPGA prototyping

  • AXI4-Lite interface

    Spec done, building

    Handshake logic and address decoding for a register-mapped interface, with a close eye on latency, backpressure and timing edges.

    Verilog HDL, simulation testbenches

  • FPGA and embedded projects

    In progress

    Bringing several boards online and validating peripherals, then writing embedded firmware and drivers and chasing real-time issues.

    FPGA toolchains, embedded C, logic analyzers

The lab stack

RTL and verification

  • Verilog and SystemVerilog
  • Testbench development
  • Timing analysis and waveform debug

CPU and microarchitecture

  • RISC-V ISA implementation
  • Control and datapath design
  • Pipeline and hazard analysis

FPGA and embedded

  • FPGA bring-up
  • Embedded C and assembly
  • Hardware–software co-design

Tools

  • Icarus Verilog
  • GTKWave
  • Logic analyzers

Hiring for RTL, verification or bring-up work? Let's talk.

I'm open to internships, full-time roles and collaborations on processor design and FPGA projects.

Email me Download resume